EDA News Monday December 1, 2003 From: EDACafe ÿÿ Previous Issues _____ Cadence _____ About This Issue Virage Logic's Adam Kablanian on the business and technology of IP _____ November 24 - 28, 2003 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ Conversing with Adam Kablanian, President and CEO at Virage Logic Corp. is easy. He's straightforward and relaxed, at least to the casual observer: "I was born in Syria and went to an Armenian high school there. The reason I'm here in the U.S., however, is because early on I developed a passion for physics. I wanted to know how physics worked, how astrophysics worked. And even though I could have gone to Aleppo to earn my doctorate and make a living, my dream was always to come to U.C. Berkeley to study and to become a physics professor." Kablanian did earn his degree in physics from Berkeley, in 1983, but veered from his dream of teaching to pursue a more pragmatic career in product development in Silicon Valley. "After graduating, I went to work at Xicor, which was one of the first companies to branch off from Intel. At that time, they were making memories. I spent two years in their Quality and Reliability group, which is where I learned that if you want to make a difference in a product, it has to be in the design - it's in the design where the innovation and new ideas lie. So I transferred to the design department at Xicor and began to pursue a graduate degree in Electrical Engineering from the University of Santa Clara." He completed his masters in 1991, but admits that the years leading up to his graduation were difficult. "The main focus for me during those years was my career and my family. It was very, very tough to get up early in the morning to attend classes at Santa Clara, to pursue my career, to have a family, and to keep up with my studies. It was a relief when I was finally done." Kablanian spent five years at Xicor, followed by a brief sojourn at LSI Logic, and then spent five years at Waferscale Integration (WSI) where he spent his time "doing lots of Flash and EPROM memory design." After WSI, he went back to LSI in a consulting capacity, and it was at this point that Kablanian decided to found Virage Logic. He says, "By that time, I definitely had a great deal of expertise in memory design, while my time spent in consulting had helped me to figure out how to leverage my expertise. When we founded Virage, there were only a few companies in commercial IP. It was a fairly new industry at the time, but I felt that [the IP business model] was the best way for me to scale what I knew best. Alex Shubat, our CTO, has been with me since the beginning of the company in 1996. Although Alex had been at WSI for 10 years, where he was Director of Engineering, I convinced him that we could bootstrap Virage and more importantly that there was a market demand for embedded memory. It's true that the economic situation in 1996 was a factor [in our decision to move forward with the company], but it was really the need that I had observed in the market for more embedded memories in SoCs [that prompted us to found Virage]." "The first two years we were in business, we were mainly a consulting operation, providing services to companies, not products. As we worked with our customers, we developed the necessary software tools for our memories and we began to productize our IP - often with the help of those customers. For those first two years, our earnings were not substantial, although we were always able to meet the payroll for the 8 people in the company." Kbablanian says that Virage got the break they were looking for in 1998: "That was when PCM Sierra became our first IP customer, purchasing our .25-micron product. And they helped us to productize that IP, although the product was not yet robust. We were lucky to have PMC Sierra there to give us our first start in the memory compiler business." "In the IP business, nothing really happens in a rational way. We didn't have a business plan, we only had a vision which was to build the best products. Our concept was to become the embedded memory company. At the time, there were many, many library companies. The [wisdom at the time said that], in order to be successful, you had to be providing embedded memory and I/O, but we said we had to only provide embedded memory as our focus." "Something else that helped us at the time was the growth of the Internet. There was lots of demand in the late 1990's for more bandwidth, more switch fabric devices and other components, all of which needed more memory on-chip to get to the required performance. That helped to increase the demand for embedded memory and for our products - 1998, 99, 2000 were very good years for us. We had good traction with PMC and with MMC Networks, now part of AMCC. These were our first two customers in the networking and communication space. The rest of the companies in that industry were impressed that PMC and MMC were doing business with us, which in turn allowed us to gain traction in the market." It was in this time frame that Artisan announced a new business model, one that offered 'free IP' to the industry. Kablanian says, "We never thought that the Artisan model was a big deal, although Artisan definitely took advantage of their IPO and a tremendous amount of cash. They thought they could eliminate the competition by providing free IP to users. In 1998, when they introduced that model, we were just introducing our first product, and we were actually growing our market while Artisan was giving things away. They had an established relationship with TSMC and other foundries, which made it somewhat difficult for us to convince our customers that we were offering quality. However, here we are today, still working successfully. I firmly believe that for any company that provides value with a differentiated product, you can succeed even if the competition is giving away product for free, or giving the perception that the product is free." "In early 1999, we received our first corporate funding - Round B raised close to $3.5 million. All of the companies involved wanted to collaborate with us on the technology side for both strategic and financial reasons. In late 1999, we received $10 million from Crosslink Capital. Mike Stark was on our board and was instrumental in attracting additional board members as we went through that very critical period. I'm very happy to say that they are all still on the board today. Six months later, we went public." "[It's important to note that] any company that has a large addressable market could go public then, or now, although the costs of course are different now. Publicly traded companies spend $3 million a year to remain public. If that's 15 percent of total revenues, the costs are not justified. You need to have scalable revenues because the auditing fees and the costs of director and officer insurance have really skyrocketed, [not to mention] the costs of being compliant with Sarbanes-Oxley. You have to hire external consultants to help you with that compliance, and more lawyers, and pay the higher charges of certifying the results. It all adds to the costs of running the company, plus the time management spends to make sure that things are in compliance. All of this takes away from time for pursuing additional revenues." "We went public in 2000 because we had real customers, real products, and we were making money, but we went public just after the burst of the Internet bubble. At the time, our investors told us that they were not pursuing 70 percent of their prospects, but that we shouldn't worry because we were definitely going public. After we went public in August 2000, we had parties in 5 different locations. By that time we had facilities in Fremont, California, in Bellevue, Washington, in New Jersey, in India on the outskirts of Delhi, and in Armenia. I visited each location over the course of the next year and celebrated with the local workforce and their families." "When we started the company in 1996, and were just a consulting shop, it was very difficult to recruit engineers in Silicon Valley. We had no funding, just an idea, and recognized that there was a big-time shortage of engineers. So we looked for talent from as far away as South Africa and India. We knew that for us to be successful in the long run, we had to plan for the long run. So even before we had funding, we were planning to diversify outside of Silicon Valley. Our universities here in the U.S. were not graduating a lot of technical people - which is a problem because you can't build a technical society without engineers and scientists. Now, today, we need to emphasize more science and engineering in the universities, although it's hard to motivate students [to pursue these disciplines] when, with the downturn, there are few jobs for engineers." "Today, cell phones and graphics chips are driving 90 nanometers. At 90 nanometers, it costs $20 to $30 million to design and produce SoC chips. You're not going to see too many fabless companies with that level of R&D investment. It's going to change the way chips are designed and produced. You're going to see more and more movement towards programmable chips, products from Xilinx or Altera or LSI with their structured ASICs, where most components are pre-fabricated and designed, and you get quick turnaround by designing onto a platform. That's also a reason you'll see more migration of hiring to India and other places. If you look at a $30 million cost for SoC development, $20 million of that is engineering salaries. Moving off shore will reduce the R&D barrier for designing chips. It's really all being driven by the economics [of the situation]." Turning to current issues, Kablanian says Virage went through a transition plan a year ago: "We decided to extend our offerings beyond embedded memory. Our customers were asking us to offer more physical IP. At this point, we have over 220 customers, and the company is very global in nature. We have customers in Malaysia, China, Japan, Europe, and Israel. We've had to develop a global infrastructure to help us serve that customer base." "And we're happy to be working today in 90 nanometers - we've got 15 customers signed up, have silicon-proven products, and our programmable standard cells will help. LSI's RapidChip technology is really good with our programmable standard cells. We don't have a programmable platform, but we have the elements to make that technology viable." Kablanian pauses before answering, 'Where will we be in 5 years?' "The IP industry is going through a rapid consolidation today, and we believe we'll be approaching a new maturity level over the next 5 years. There are many forces at work in the industry - forces that come through the customers and through the food chain. That's why we want to branch out beyond memory and look at the entire IP world with our new platform strategy. It's an exciting era, one that I view as offering a great deal of potential. I foresee that today's chip will be tomorrow's IP." "[But in fact], so much changes in just one year, it's really difficulty to have a 5-year plan. We do have 3-year planning with our financial model - revenue projections, what type of products we will need to design to meet 65 nanometer and 45 nanometer customer requirements. On the business side, we're recognizing that the industry will go through further consolidation. So we look at different scenarios in terms of how we position the company. That's certainly my vision for the company. We do have definite companies that we'll be pursuing in the next year in order to create bigger value for the industry and for our shareholders." Kablanian says, "We always see ourselves as an extension of our customers' R&D - they're extending their R&D resources to tap into commercial IP. Our IP is very custom, never cookie cutter. However, everything we build is useful for many people. The leverage with IP comes with finding the larger customers who can use that standard form. However, there will always be specialized structures for specific applications. You can't just have a product and hope that it becomes commercialized, [neither can] you just lock up the marketplace and work on your next product. The demand and the standards are always changing. The dilemma - or strength - for IP companies is that they need to continuously innovate. In fact, it's only those who continue to innovate who will continue to succeed. We have committed over 35% of our revenue in recent years to R&D. That's a key metric for us to remain as a star IP company." "There's actually a second way of looking at this. Our customers want us to be successful. In order for them to manage their own IP costs, they need to compromise and allow us to use our products in the larger market. Also, they often want us to provide them with standard products, but to maintain and improve those products over time. If something we provide to them is just custom, they increase the risk of the IP not being maintained or becoming a niche product - which means it would lose momentum for the next generation. It's to the benefit of our customers to work with us to standardize IP, to help us to reduce the cost of providing IP. Yes, you could describe the situation as one where there is a virtual R&D department that spans across multiple corporate firewalls." "If you look at large IDM manufacturers today, every one of them has a different way of designing chips. For us, that means we need to make our interface with our customers such that they feel that we are an extension of their internal culture. This is the challenge that every IP company faces. Our customers look to us to provide quality IP - the most important thing being that the silicon has been validated or proven. That's almost a bigger value than the IP itself. In that sense, it benefits IP companies to come up with a way to certify the quality of IP. It's only then that we will be able to grow the IP market. Certification - something like an ISO 9000 - would provide a competitive advantage and an industry wide benefit. We could see FSA driving that effort. Certainly many people are reviewing the issue and I'm encouraged to see that it's an issue being discussed. My hope is that this will benefit not just us, but all of our colleagues in that space." "Today, with the world being what it is, it's very difficult to enter the market. But, there are still great opportunities out there. Even today, a company can grow if you're passionate about your work and if you can provide value to your customers, value not available from your competitors. Everything I do, I'm passionate about - my work or my co-workers or my family. Everything I do is because I'm pursuing my passion." Industry News - Tools and IP Accelerated Technology announced that its Nucleus RTOS has been used by Garmin International to develop the CNX80 navigational GPS designed for general aviation. Per the Press Release: "The CNX80 GPS allows a pilot to file a flight plan, receive clearance, and program the approved flight plan. The CNX80 GPS includes the industry's first certified wide area augmentation system (WAAS), which dramatically improves the accuracy, integrity and availability features of the GPS and provides for a safer flight of an aircraft. Garmin developers looked for an RTOS that they could certify through the FAA to meet the airborne software requirements from DO-178B for Level B software. Certification requires adequate documentation that every decision point in the source code is fully tested to ensure safe operation of an aircraft. Developers tested the Nucleus PLUS kernel and received FAA certification with no changes required." AirDefense, Inc. announced that Synopsys, Inc. is using AirDefense tools to "protect its wired corporate network from unauthorized wireless LANs and enforce security and management policies across its sanctioned wireless LANs." Synopsys says its global wireless LAN connects 81 offices in 11 countries. Van Nguyen, Director of Security for Synopsys, is quoted in the Press Release: "Synopsys evaluated the market for WLAN monitoring, including AP switching and scanning vendors, and quickly recognized the need for a dedicated sensor- based system with centralized policy monitoring and enforcement. Only AirDefense could provide this level of security and policy enforcement. Synopsys chose AirDefense for their robust intrusion detection engine that does not overwhelm you with false positives." HDL announced a "major update" to its family of functional verification tools on November 17th - @Verifier and @Designer Version 4.0 - which the company says delivers "technology to significantly improve the productivity of design and verification teams working with the new assertion languages of Accellera PSL and SystemVerilog." Ravi Selvaraj, Senior Director of Engineering at SiNett Corp., is quoted in the Press Release: "In establishing our verification methodology, we determined from the outset that the use of assertion-based methods would be key to our delivering high density, innovative silicon solutions for the wireless LAN market. Our engineering team will be making extensive use of PSL to create a robust verification flow. SiNett selected @HDL based on the PSL support in their @Verifier product, as well as the tightly integrated assertion and simulation debugging capabilities in @Designer. We can see that the @HDL Assertion Studio technology will be instrumental in developing effective assertions for validating our RTL in a timely fashion." Mentor Graphics Corp. announced a new class of design kits for the Xilinx Virtex-II ProX family of FPGAs. The Mentor design kit provides designers with high-speed verification models written in ICX-SPICE to be used with Mentor Graphics ICX PCB design verification environment. The companies say that designers can now implement "the world's fastest FPGAs on their PCBs using Mentor's integrated design entry, place and route and signal integrity solution." Jerry Banks, Director of Global Alliances at Xilinx, is quoted in the Press Release: "Mentor Graphics has reduced the cost and complexity of multi-gigabit signal integrity analysis by fully integrating its SPICE and S-Parameter solution directly within its PCB design environment. Users should benefit from a robust design with a reduced number of board spins and a higher PCB production yield by having accurate verification models for our multi gigabit Virtex-II Pro X devices." Prosilog SA announced that it has been selected by the European Space Agency (ESA) for the implementation of a complete design flow, from SystemC transactional level down to RTL implementation. Laurent Hili, VLSI/ASIC Engineer in ESA's Microelectronics Section, is quoted in the Press Release: "ESA has decided to work with Prosilog to investigate a new system-on-chip design methodology based on the SystemC language. The objective of this partnership is also to assess new concepts based on the OCP-IP protocol, allowing fast IP integration and reuse. We want to be able to perform architectural trade-offs, try several partitioning approaches between hardware and software, and choose between different memory schemes and bus topologies. The cooperation with Prosilog will allow us to address all of those challenging topics." Synfora, Inc. announced November 17th its PICO 'Algorithm-to-Tapeout' synthesis. Per the Press Release: "PICO bridges the SoC design productivity gap by enabling the automatic generation of optimal synthesizable RTL from ANSI C algorithms. The technology consists of (a) configurable RTL IPs designed for efficient implementation of complex algorithms compatible with existing RTL-to-GDSII tools - this compatibility ensures easy integration with the other blocks in the design; and (b) architectural exploration and configuration tools that create a Pareto optimal list of implementations within user-defined constraints, as well as synthesizable RTL - all in a matter of hours or days, instead of weeks or months. Unlike previous alternative solutions delivered either as an EDA tool or IP, Synfora's PICO technology combines advanced parallel compiler and synthesis capabilities linked to configurable RTL IP. This combination makes PICO especially well-suited for designers who need to build custom blocks with significant amounts of parallel processing." I spoke with Simon Napper, President and CEO at Synfora, by phone on November 17th. He told me, "Synfora was founded in January 2003 by a team from HP labs. Hewlett Packard owns the patents for the PICO technology, but we have been given the license to use the patents and the PICO source code. The PICO project at HP was chartered to produce custom application engines directly from C algorithms for embedded applications such as audio/video or printing. In a typical C program, there are certain parts of the program that are control intensive and certain parts that are compute intensive. PICO's underlying IP addresses both control and compute intensive blocks. PICO gives you a whole series of points that allows you to decide how small or fast an RTL design you want for the algorithm. From a user perspective, PICO provides a set of tools that allows him/her to explore the design space such that they can take a single algorithm and have different implementation points." "We define algorithm-centric design as being characterized by end products such as highly integrated devices, for example, digital cameras, printers, game consoles, cell phones, and set top boxes. These products implement a range of standard algorithms. For example a cell phone with a camera uses a JPEG algorithm to compress images, a DVD player implements an MPEG2 algorithm to decode the bit-stream from the DVD disk. Designers are faced with the challenge of differentiating their end products when the starting point is an industry standard reference algorithm. This is where PICO's ability to go from algorithm to tapeout is critical." "When we say we're providing C to RTL synthesis, people often roll their eyes. They think they're seeing another lemming about to fall off the cliff. But once they see our technology, they respond, ' PICO does sound different. Show me.' We think we've solved the problem - the problem of going all the way from algorithm to tapeout. Right now, we're focusing on articulating our step-by-step implementation plan." "Among the many issues we're focusing on right now is productivity. Synopsys made RTL-based design the mainstream back in 1995. People have been struggling to move up to the next level of productivity since that time, but so far they have not succeeded. We're focusing on the algorithms that will allow people to move from C down to RTL - something that people have tried to do, but have failed to achieve [up to now]." "A lot of engineers in the U.S. and Europe are realizing that they need to improve their productivity [in the face of increased outsourcing]. Right now, it's not clear how many RTL gates can be laid down by an engineer in a week - maybe a couple of thousands - but we know that [using our tools], you can move to 100,000 gates per week. People are seeing that they can boost their productivity and bring design costs down at the same time. They're able to move beyond just writing RTL. You can get very smart people to write RTL in several places around the world." "To make a move of this sort, an industry must be in need of three things - dissatisfaction with the status quo, which will overcome the fear of change, a vision of where the trends are moving to, and an implementation plan for how those [goals will be reached]. We believe that the downturn and increased use of outsourcing RTL design has created the dissatisfaction with the status quo, and we believe that PICO promises significant productivity gains and design cost reduction. We plan to roll out a series of products that will provide a step-by-step method of reaching the goal of low-cost, highly integrated smart electronic products." Coming soon to a theater near you IEDM 2003 - The IEEE International Electron Devices Meeting is just around the corner, December 7th to 10th at the Hilton in Washington, D.C. This is one of the important annual gatherings for all of those interested in cutting edge research, technical advancements, and dialog across a spectrum of academic and industrial R&D. Organizers say that 221 papers were selected from close to 700 submissions, sent from 24 different countries. They also say that Sunday's short courses and Monday's plenary talks are of particular interest - On Sunday, "Interconnect Scaling: From Technology to System Design" and "Silicon+: Augmented Silicon Technology." On Monday, "Ambient Intelligence - Key Technologies in the Information Age," "Requirements and Strategies for Semiconductor Technologies for Mobile Communication Terminals," and "Nanotechnology Needs Today." Anyone who has ever attended IEDM knows, it doesn't get much better than this. ( www.his.com/~iedm ) Accellera Symposium - Coming up on December 4th in Santa Clara, CA, the symposium will allow participating companies to demonstrate their SystemVerilog-based products and to discuss their SystemVerilog support. Accellera Technical Chair Members will be available for private discussions, and demos of SystemVerilog-based tools from various EDA companies will be featured. ( www.accellera.org ) SystemC Courses - Summit Design announced that it is partnering with Willamette HDL to offer SystemC courses with Summit's Visual Elite system-level design and verification environment. Rami Rachamim, Director of Marketing at Summit Design, is quoted in the Press Release: "SystemC usage is growing rapidly and training and education are critical for the support of our customers in this wave of adoption. The language-based training group at WHDL has an excellent reputation within the industry for delivering top-notch SystemC training." ( askus@sd.com ) SNUG Europe - An annual meeting of Synopsys users from throughout Europe, this is an open forum where users can discuss problems and exchange solutions. Synopsys says, "The program is highly technical and is primarily developed by users." Synopsys also says that a new technical chair has been named, Tobias Thiel of Motorola GmbH, and that the meeting will be held May 6th and 7th in Munich - rather than in conjunction with DATE in February in Paris, which has been the standard in the past. ( www.synopsys.com ) DAC 2004 Student Design Contest - It's not too early to start laying down your plans to attend DAC 2004 in San Diego, CA, and to be involved in one way or another with the ever-popular Student Design Contest that takes place at the conference each year. The deadline for contest submissions is looming - December 12th - so if you're a full time undergraduate or graduate student, you'd better get cracking. Go find a professor to help you navigate the submission process and try it out. It could be a lot of fun. Alternatively, if your station in life is such that you might see fit to serve as a corporate sponsor, there's no time like the present to step up and offer financial support. Your generosity will play well with your constituencies and, more importantly, will help to foster innovation and enthusiasm among the designers of tomorrow. Corny sentiments perhaps, but can you remember back when you were in school and how thrilled you would have been to have been able to participate in an industry event like this one? Come on, you're not that old - pitch in and help. ( .) Newsmakers Cadence Design Systems, Inc. has signed a memorandum of understanding with the Ministry of Education to develop China's first national IC design training program, which sets up the framework for the 'China National IC Design Talent Incubation Project.' The program will initially focus on nine universities. The government's target is to train 300 students per year, per university at the master's and doctorate levels. Cadence says it will provide support for the initiative, from IC design and EDA courses to jointly developed design projects. Ray Bingham, President and CEO at Cadence, is quoted in the Press Release: "We are extremely proud that the Chinese government has chosen Cadence to help China build a strong foundation as it becomes a global leader in IC design. We are also particularly honored that the government has chosen Cadence as its sole partner to provide EDA technology and training. At Cadence, we share the same vision as the Ministry of Education - to nurture IC design talent in China - which will ultimately help grow our presence and leadership position in China." In the category of ... Big guns at the OK Corral So, I'm talking by phone with Dennis Brophy, Chairman of Accellera, and he says, "There's been a big gap down in the area of physical design kits because of the lack of standards in this area. Whether you're a supplier or a semiconductor company or an EDA vendor, we know we would all win if there could be some sort of standardization in this area. Our new OpenKit initiative is set to do this. Nick English is serving as the Chair of OK. He's been involved in the past in standards efforts, he's been in the industry for a long time, and he knows that a number of companies have recognized a problem here. He has a great understanding of the issues and, as an independent person, it's much easier for Nick to go around and talk to all of the constituents in a non-political way. Now he has to carve out Steps 1, 2, and so on, and work for consensus on what the issues are that need to be addressed." The funny thing was, I already had an appointment to talk with Nick English about this very thing. Graham Bell, Director of Marketing at Nassda, had suggested the previous week that I talk to Nick because he's driving the effort to address issues that are near and dear to Graham's heart. So several days later, I was in on a 3-way phone call with both Nick and Graham. Nick said, "The subject of design kits is a huge area. Currently, they're tool and vendor specific - foundries, EDA vendors, internal design groups all put out design kits and designers ultimately have to use these things. We know that a lot of the issues surrounding design kits can be understood by looking at custom digital design. The most widely used and best understood design flows are in digital. So, initially we're going to target digital design to make rapid progress in scalable areas, and then we hope to move quickly to analog and RF design as well." "Currently, we're targeting three areas. First is front-end design format information, the symbols and schematics that help designers capture design information, the things that move around between design kits. Second is the standardization of data sheets, examining the same information from various foundries and [standardizing] what the device models look like on paper. Third, we're looking at back-end design, although it's not clear yet what our approach should be here. Perhaps we need standards regarding the fundamental drawing primitives, or standardizing on design rule formats, or standardizing on the pictures used to portray devices and dimensions." "It's important to note that we're not trying to standardize processes - that's simply not feasible. The foundries believe, however, that there's value in what we're doing, in having a standard design kit that everybody knows, a design kit that they can populate with data as fast as they can get it. We know it's always going to be a chore to migrate between foundries. Even if you look at vertically integrated companies like Intel, or IBM, or TI, or Motorola - they'll tell you it's a chore to move between fabs. We're not going to be able to make that drastically easier, but we do believe we can help with the nomenclature, the data formatting, the non-rocket science nuisances that that designers deal with every day. Anyone who's developing or using any kind of tools, anyone who needs modeling for the tools they're working on, anyone who's designing using predictions of performance of circuits cares - these are the people that care about these issues." "You can get a better understanding of what we're doing here by going to the Accellera website and looking at the documents, including the Design Objective Document, which meets Accellera's requirement to position the problem and describe why it's important to address it. It's a good piece of work with significant contributions by industry folks that have been a part of the process and who are credited in the document. And, Graham's been monitoring our work because it's related to the Nassda technology. We've had four technical meetings so far, and will continue on a roughly monthly basis." At that point, Graham asked Nick, "How would you characterize where we are with custom versus traditional ASIC flows, which have a lot of smoothness built in by now?" Nick said, "That's a very important point. First of all, compared to transistor or custom design, synthesis based top-down design is well understood. Synopsys clearly has the dominant market share there, while there are various companies in verification and the back-end. All of that smoothness has ad hoc point tools that work together pretty well down to the cell library level. But from the bottom-up perspective, all of the information used by those flows is built up in a much less smooth fashion. There are multiple variations on simulators or Spice models, which are all created bottom-up, based on piecemeal information and rapidly changing process refinements, etc. Foundries, EDA vendors, and internal DA groups all have a hand in design kit work and that's where we're hoping to begin to clean up the problem." "The digital designers may be asking, 'What's the problem? Everything's working just fine.' But, in fact, it was Jim Hogan who said that, just once in his career, he'd like to see a custom design done with anything near the ease with which digital design is done. If we do our jobs well with the OK initiative, we'll be invisible to the top-down flows, but we'll make them work more seamlessly, more productively, with fewer problems along the way." "We're trying to move standardization from a de-facto process to a formal control process, which will ease adoptability. Right now, we're looking to come up with something by DAC 2004 - we should have something to announce in that timeframe within the three areas we've selected to work in first. We've chosen to work through Accellera because, despite their language wars, they've proven they can get things into the IEEE standards process relatively quickly, and we believe IEEE is the appropriate ultimate standards body of our industry. We are looking to the Accellera process to help us obtain the IEEE sanctions we need." "Maybe our industry is maturing a bit, because we've tired of doing things the wrong way a lot of the time. Now we're asking that people please join with us, make their opinions known, and have fun being part of this process." Graham added, "Nobody wants to be part of just one more standards committee, nobody wants to be on a committee to build a camel. Today, I think people understand that there's a better way of doing things in this area. They're looking for better efficiencies and they're tired of reinventing the wheel." --Peggy Aycinena is a Contributing Editor and can be reached by clicking here . You are registered as: [dolinsky@gsu.by]. CafeNews is a service for EDA professionals. EDACafe respects your online time and Internet privacy. To change your newsletter's details, including format and frequency, or to discontinue this service, please navigate to . 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